1. Technical Field
The present invention relates to methods of fabricating a semiconductor device, and more particularly, to methods of fabricating a semiconductor device using a sacrificial layer.
2. Discussion of the Related Art
Recently, research is being carried out into increasing process margins in semiconductor fabrication processes on a semiconductor device in order to electrically connect discrete elements to one another on a semiconductor substrate, using interlayer insulating layers. One approach involves the use of a chemical mechanical polishing (CMP) process on the interlayer insulating layers. The semiconductor fabrication processes include a photolithography process, an etch process, and a deposition process. The interlayer insulating layers are formed on a semiconductor substrate to cover discrete elements and isolate them. In general, interlayer insulating layers have been used with excellent planarization characteristics through the CMP process for removing step height differences between discrete elements and the semiconductor substrate, and between the discrete elements. The planarization characteristics of the interlayer insulating layers may improve process margins of a photolithography process, an etch process, and a deposition process in a given design rule. However, thicknesses of the interlayer insulating layers on the overall surface of the semiconductor substrate cannot be maintained uniform by the CMP process. In addition to intrinsic step height differences of the discrete elements, additional step height differences are formed on predetermined regions of the semiconductor substrate due to intrinsic characteristics of a polishing equipment system used during performing the CMP process. The intrinsic characteristics depend on a pad, a carrier head, and lifetime of consumptive conditioners of the polishing equipment system. As such, the CMP process may reduce process margins of photolithography, etch and deposition processes.
In one approach to these familiar problems, U.S. Pat. No. 6,599,838 to Tsu Shih, et. al (the '838 patent), which is incorporated herein by reference, discloses a method for forming metal filled semiconductor features to improve a subsequent metal CMP process. According to the '838 patent, the method includes preparing a semiconductor processing substrate on which first and second dielectric insulating layers are sequentially disposed. The first and second dielectric insulating layers have openings. The second dielectric insulating layer is formed to have a removal rate ½ or less than that of the first dielectric insulating layer in the CMP process. Metal is formed on the second dielectric insulating layer to fill the openings. Then, the CMP process is performed on the metal until the second dielectric insulating layer is exposed.
However, the method cannot planarize the upper surface of the semiconductor substrate by using the second dielectric insulating layer. This is because the upper surface of the first dielectric insulating layer before performing the CMP process may not be planarized by the method. Further, a thickness of the second dielectric insulating layer on the overall surface of the semiconductor substrate may not be maintained uniform due to intrinsic characteristics of the polishing equipment system after performing the CMP process.